Integrated circuit chips have grown in size and packing density to meet user demand for more functions and storage capacity at lower cost. With this development, advantages in distributing power to the chip become important.
A common approach is to incorporate a power distribution network into the chip itself. However, the power busses tend to be large and the chip size must be increased, or functional space sacrificed, to accommodate them. Aside from the usual cost disadvantages, an increase in the size of a chip that is already comparatively large may require an expensive, or non-standard, packaged design. Correct use of these tradeoffs is becoming an important ingredient in the ability of a manufacturer to produce cost competitive integrated circuit devices.
An alternative to increasing the chip size to accommodate the power distribution network is to distribute the power off chip and introduce power (and ground) at more than one bonding site on the chip. However, each new bonding site consumes a pin and it is desirable to avoid multiple pins for power as well as to avoid separate power distribution means on the mounting board.